In general, data transmitters (i.e., devices having digital data outputs) need to deliver digital data to other devices (i.e., data receivers), often at high rates and often over serial communication channels. Frequently, the clock rates (speeds) used for communication between devices is sufficiently high that propagation delay issues exist. Unknown, varying or excessive propagation delays pose a challenge with respect to synchronizing receivers and transmitters, maintaining synchronization, and with respect to reliably transmitting digital data. The serial communications protocol used in such environments, as well as the apparatus and methods for implementing such protocol, must incorporate a propagation delay-tolerant approach to synchronization between transmitter and receiver. Furthermore, the apparatus and method must be tolerant to signal dispersion and variations in signal generation.
Currently, the clock speed for communication between devices on separate chips is typically about 125 MHz, while a speed of about 375 MHz might be used when the devices are on the same chip. Faster speeds are likely in the future. At these speeds, the devices must accommodate a considerable amount of variability in signal propagation delays. Differences and changes in signaling delay may be caused, for example, by variations inherit to the fabrication process, time-varying environmental conditions, power supply variations, and other factors.
Because cost is an important consideration for commercial products, the need exists for a serial communications protocol and interface that is compatible not just with high-priced products, but also with lower cost products such as low-cost field programmable gate arrays (FPGAs) which are often used to implement devices such as transmitters and receivers in digital systems.
A need also exists for an interface and interfacing method which permits serial data communications in which a transmitter can adjust its transmission rate to that a receiver can accept.